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Explain about BatchPreparedStatementSetter?

Asked by Amit Dubey in Computers & Technology at 10:23 PM on December 08, 2008

ayisha's Answer

public interface BatchPreparedStatementSetterCallbac k interface used by the JdbcTemplate class.

This interface sets values on a PreparedStatement provided by the JdbcTemplate class for each of a number of updates in a batch using the same SQL. Implementations are responsible for setting any necessary parameters. SQL with placeholders will already have been supplied.

Implementations do not need to concern themselves with SQLExceptions that may be thrown from operations they attempt. The JdbcTemplate class will catch and handle SQLExceptions appropriately.

Answered at 10:45 PM on December 08, 2008

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Explain about RowCallbackHandler and why it is used?

Asked by Amit Dubey in Computers & Technology at 10:23 PM on December 08, 2008

ayisha's Answer

In order to navigate through the records we generally go for ResultSet. But spring provides an interface that handles this entire burden and leaves the user to decide what to do with each row. The interface provided by spring is RowCallbackHandler. There is a method processRow() which needs to be implemented so that it is applicable for each and everyrow.
Sources:
http://faqs.javabeat.ne t/spring/spring-interview-questions -faqs-5.php..

Answered at 10:41 PM on December 08, 2008

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What is the c language. what is the c language. what is the c language.?

Asked by RUMIT GUPTA in Computers & Technology at 10:05 PM on December 07, 2008

ayisha's Answer

The language(s) of which the interpreter has a complete understanding and from which she or he works. Interpreters often have several C languages.

Answered at 11:15 PM on December 07, 2008

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Explain me about CAS?

Asked by Gaurav Montu in Computers & Technology at 7:33 AM on December 07, 2008

ayisha's Answer

CAS,(column address strobe ) a signal, or strobe, sent by the processor to a DRAM circuit to activate a column address. DRAM stores data in a series of rows and columns, similar in theory to a spreadsheet, and each cell where a data bit is stored exists in both a row and a column. A processor uses CAS and RAS (row address strobe) signals to retrieve data from DRAM. When data is needed, the processor activates the RAS line to specify the row where the data is needed, and then activates the CAS line to specify the column. Combined, the two signals locate the data stored in DRAM.

Answered at 4:36 PM on December 07, 2008

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What is a Pseudocode explain?

Asked by Abhijit Naya in Computers & Technology at 9:36 PM on December 07, 2008

ayisha's Answer

An outline of a program, written in a form that can easily be converted into real programming statements. For example, the pseudocode for a bubble sort routine might be written:
while not at end of list
compare adjacent elements
if second is greater than first
switch them
get next two elements
if elements were switched
repeat for entire list
Pseudocode cannot be compiled nor executed, and there are no real formatting or syntax rules. It is simply one step - an important one - in producing the final code. The benefit of pseudocode is that it enables the programmer to concentrate on the algorithms without worrying about all the syntactic details of a particular programming language. In fact, you can write pseudocode without even knowing what programming language you will use for the final implementation.

Answered at 11:18 PM on December 07, 2008

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What is CAS Latency?

Asked by Gaurav Montu in Computers & Technology at 7:33 AM on December 07, 2008

ayisha's Answer

CAS latency is short for Column Address Strobe latency.
CAS latency is the time (in clock cycles) required to access a column of memory on a DRAM memory module.
A CAS3 rated memory module requires 3 clock cycles to address a column of memory, where a CAS2 rated memory module can accomplish the same task in only two clock cycles.
Three steps are required to address DRAM on a memory module, such as a DIMM:
Memory bank selection
Memory row selection (Row Address Strobe)
Memory column selection (Column Address Strobe)
CAS latency is sometimes abbreviated as CL.

Answered at 4:34 PM on December 07, 2008

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What is DDR SDRAM?

Asked by Gaurav Montu in Computers & Technology at 7:33 AM on December 07, 2008

ayisha's Answer

DDR SDRAM is Double Data Rate SDRAM.
DDR SDRAM is an improvement over regular SDRAM, also known as SDR SDRAM (Single Data Rate SDRAM).
DDR SDRAM doubles the bandwidth of SDR DRAM by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.
DDR SDRAM is being supplanted by DDR2 SDRAM.

Answered at 4:33 PM on December 07, 2008

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What is DDR2 SDRAM?

Asked by Gaurav Montu in Computers & Technology at 7:34 AM on December 07, 2008

ayisha's Answer

DDR2 SDRAM, an abbreviation for double data rate two synchronous dynamic random access memory, is a type of a random access memory (RAM) commonly used in personal computers and various digital electronics today. This offspring from the SDRAM (synchronous dynamic random access memory), a part of DRAM (dynamic random access memory), is like an evolution from the DDR SDRAM; it can operate the external data bus twice as fast as its predecessor. This was possible by abandoning the original clock rate of the DDR, and operating the memory cells at half the rate. If the DDR2 was clocked at the same rate, the performance would be worse.
The DDR2 was first introduced in 2003 at 200 MHz (PC2-3200) and 266 MHz (PC2-4200), but it failed to outperform the original DDR due to a latency problem. Nonetheless, a combination of the original DDR technology being at a speed of about 266 MHz (but 533 MHz effective), the JEDEC (Joint Electron Device Engineering Council) Solid State Technology Association not standardizing the faster DDR chips, and a release of newer DDR2 modules with lower latencies, the DDR2 eventually began the better solution. By the end of 2004, the DDR2 really began to compete against the standard DDR.

Answered at 4:32 PM on December 07, 2008

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Explain me what is DIMM?

Asked by Gaurav Montu in Computers & Technology at 7:35 AM on December 07, 2008

ayisha's Answer

Dual Inline Memory Module or DIMM is a series of Random Access Memory (RAM) chips mounted on a small printed circuit board. The entire circuit collectively forms a memory module. DIMMs are commonly used in personal computers, servers and high-end workstations. The DIMM makes physical contact with the data bus of the computer through teeth like connectors that fit into a socket on the mother board.
The earlier memory modules were known as SIMMs or Single Inline Memory Modules and had a 32-bit data path. DIMMs on the other hand use a 64-bit data path, since processors used in personal computers including the Intel Pentium have a 64-bit data width. Since SIMMs can handle only 32-bits at a time, they were always used in matched pairs to fully utilize the processing power of the CPU. DIMMs were developed to rectify this inefficient method of installing memory modules.
SIMMs have an identical pair of electrical contacts one on each side of the module and the processor can access the SIMM through either side. Hence the connectors used in a SIMM are redundant contacts, whereas the DIMM has unique contacts on either side of the module and it makes much better use of the connectors.
DIMMs that implement error detection and correction are known as Error Correction Codes enabled DIMMs or ECC DIMMs. Apart from the data bits, these DIMMs use extra bits for ECC. While there are many types of ECC schemes, the SECDED or Single Error Correct - Double Error Detect scheme is the most common and uses an extra 9th bit for every byte of data.
DIMMs come in various standard sizes known as form factors. Earlier DIMMs came in sizes of 1.5 inches and 1.7 inches. Later on when rack-mounted servers became common, these DIMMs had to be squeezed into a narrow space and hence the DIMM sockets were tilted to an angle to accommodate the memory modules. To address this issue, the next standard of DIMMs had a low profile height of 1.2 inches eliminating the need for angled sockets. When servers became even smaller, the sockets were again angled to accommodate the LP form factor. This further led to the development of the VLP or Very Low Profile form factor with a height of a mere 0.72 inches. The Mini-DIMM, the SO-DIMM and the VLP Mini-DIMM are the other popular form factors.

Answered at 4:31 PM on December 07, 2008

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What is DDR3 SDRAM?

Asked by Gaurav Montu in Computers & Technology at 7:34 AM on December 07, 2008

ayisha's Answer

DDR3 SDRAM (Double Data Rate Three Synchronous Dynamic Random Access Memory) is the third generation of DDR SDRAM.
DDR3 SDRAM improves on DDR2 SDRAM in several significant ways:
Higher bandwidth due to increased clock rate
Reduced power consumption due to 90mm fabrication technology
Pre-fetch buffer is doubled to 8 bits to further increase performance
The voltage of DDR3 SDRAM DIMM's was lowered from 1.8V to 1.5V. This reduces power consumption and heat generation, as well as enabling more dense memory configurations for higher capacities.

Answered at 4:32 PM on December 07, 2008

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